a wafer metrology consortium under MAGNET
According to ITRS, the expectation is that in 2018, chip manufacturers will start moving toward high-volume manufacturing (HVM) with 450mm wafers. Already today, these manufacturers are building pilot lines and readying facilities for this purpose. Israeli metrology companies plan on being at the forefront of this revolution.Read more
The primary reason of moving to 450mm is cost; the 450mm manufacturing tools must be faster to enable more dies out, Such a change lead to a concomitant requirements in significantly updated metrology tools. It is this major step in chip manufacturing which the Metro450 consortium wants to utilize as a slingshot far advancing Israeli-based metrology companies.Read more
Already today (in 2013), the large computer chip manufacturers are working on pilot lines for the 450mm wafer production. Based upon published reports, by 2018, at least some of these manufacturers will move toward high-volume manufacturing of chips on this wafer size.Read more
Israeli metrology companies are fierce competitors. How are they able to get together in such a consortium? The answer lies in the type of knowledge they share. No information is shared that is machine-specific. Details about how the measurements are done are not shared. Instead, non-core-IP is revealed. The cooperation lies in cooperation in pre-competitive issues, such as those described in the work packages.Read more
Metro450 is an Israeli consortium which is cooperating with international consortia, including G450C, based in Albany, NY, and with several European projects, such as 450EDL and 450PR under the aegis of ENIAC. Metro450 Israel welcomes additional cooperation with similar bodies around the world.
News and Events
- SEMI recently completed its annual silicon shipment forecast for the semiconductor industry. This forecast provides an outlook for the demand in silicon units for the period 2014-2016.
- Officials at the SUNY College of Nanoscale Science and Engineering in Albany unveiled its first fully-patterned 450mm wafers at a major computer chip industry conference in San Francisco
- Researchers at the SUNY College of Nanoscale Science and Engineering are taking the “notch” out of the silicon wafers used to make microchips.
In order to determine if there are defects in the production of the dies, many points on the wafer are examined. Perhaps there is a better, more efficient method for determining just how many points really need to be checked. The goal of WP2 is to find more efficient sampling strategies than exist today.
With the larger wafer size and smaller critical dimensions of the 450 wafers, damage and contamination control become serious challenges. WP 3 attempts to determine the cause of some of the damage, and researches methods to reduce contamination in order to meet stringent specifications for the 450mm wafer era.
With the move toward 450mm wafers, and the concomitant reduction in critical dimensions, the overall data and number of calculations increases dramatically. The goal of WP5 is to utilize off-the-shelf components in order to help in the configuration of a metrology-specific computer design.